1. Technical Field
The present invention generally relates to high speed data communications and, more particularly, to timing recovery for an input/output (I/O) bus with link redundancy.
2. Description of the Related Art
With advances in digital computing capabilities fueled by scaling of semiconductor technologies, demands for high-bandwidth transmission of data in systems such as servers and data communication routers continue to increase. The total aggregate input/output (I/O) bandwidth in a microprocessor for communication with devices such as a memory continues to grow. Per-pin data rates increase to keep up with these bandwidth demands, and currently exceed several Gigabit-per-second (Gb/s). The overall trend leads to a steady increase in the I/O power for microprocessors.
However, the power efficiency of these high-speed links has not scaled commensurate to the increases in aggregate bandwidth. Several factors account for this degradation in power efficiency. First and foremost, frequency-dependent losses in the communication channels do not improve as the data rate increases. This requires more sophisticated I/O circuit architectures, including the introduction of equalizers in the transmitter (TX) and/or receiver (RX), to compensate for intersymbol interference (ISI) introduced by limited-bandwidth channels. Moreover, the decrease in the bit unit interval (UI) places more stringent timing requirements in the I/O circuitry. At multi-Gb/s data rates, adjustments in the phase of the sampling clock typically must be made with a resolution on the order of picoseconds. This ensures that the incoming data is sampled close to the time within the bit interval where the voltage margin reaches a maximum. The phase adjustment can be achieved through the use of programmable phase interpolators, delay lines, and delay-locked loops, among others. Once the clock is properly aligned or synchronized to the incoming data, one or more edges of the clock can be used to sample incoming data.
In source synchronous I/O architectures, a data source (or transmitter) broadcasts a clock signal on a separate channel along with multiple bits (or a bus) of data. This technique alleviates the need for a high-bandwidth clock recovery loop, since timing jitter on the incoming data is correlated to timing jitter on the forwarded clock. At multi-Gb/s data rates, the received clock signal must be aligned to each data bit such that all bit receivers in the bus optimally sample the incoming data.
It is often desirable to have the capability to sweep the phase of the sampling clock relative to the data in order to perform link diagnostics such as mapping eye contours or measuring timing margins. This could be required to facilitate automated link maintenance to adjust for voltage or temperature drifts, or if receiver-side equalization is employed, as the ability to sweep the sampling clock phase may be required for certain equalizer adaptation algorithms. It is preferable to do so in a manner that does not interfere with the receiving and recovery of incoming data. Therefore, it is common to find a secondary data bit receiver for link diagnostics placed in parallel with the primary bit receiver such that uninterrupted data transmission can occur while still allowing for link diagnostics. In such an architecture, two phase alignment mechanisms are required. The first provides an adjustable clock phase to the primary data receiver and might not be adjusted during diagnostics. The second provides an adjustable clock phase to the secondary data receiver, and is free to be adjusted during link diagnostics with no impact on the phase of the sampling clock for the primary data receiver. This comes at the expense of receiver power and area, since the complexity of each bit receiver has roughly doubled.
Complexity in the bit receiver can be reduced if redundant data links are employed as described in the prior art. Using link redundancy, at least N+1 data links are required to transmit and receive N-bits of data while still allowing one of the N+1 links to be calibrated or otherwise adjusted at a given time. This permits continuous and uninterrupted data transmission of the N bits. Links can be taken out-of-service periodically, and the data that was being carried over that link can be transmitted over the redundant link. While out-of-service, known training or calibration patterns or data can be transmitted and received over the link to facilitate any link calibration or maintenance algorithms. If managed appropriately, each link in the N+1 bit bus can be calibrated periodically in a round-robin fashion. While a link is being calibrated or adjusted, the phase of the sampling clock to this link can be adjusted as needed for diagnostic purposes without disturbing the N-bits of data being transmitted on other links in the bus. Link redundancy reduces hardware overhead, since secondary data receivers are not needed for each bit but rather one extra receiver is needed per N links. This comes at the expense of extra physical connections (channels) between the data transmitter and data receiver.